IBM Heron (r1, r2, and r3)

Overview

IBM Heron is the workhorse of IBM's quantum fleet. It is smaller than the headline-grabbing Condor, but it is the chip IBM chose to build its production systems around, because it has the best combination of speed, qubit quality, and stability that IBM has shipped. The first version, Heron r1, had 133 qubits. Revision r2, introduced in July 2024, has 156 qubits, and r3 followed in 2025 with the same qubit count and further performance improvements.

If you are learning quantum computing and run a circuit on an IBM system through the cloud, there is a good chance it runs on a Heron-class processor. The chip also sits inside IBM Quantum System Two, the modular cryogenic platform IBM designed to house several processors in a single installation.

History and background

IBM unveiled Heron on December 4, 2023 at the IBM Quantum Summit, at the same time as the 1,121-qubit Condor. The two chips represented a deliberate change of direction: IBM said that after reaching 1,000 qubits it would focus on improving quality and on connecting processors together, not on making single chips ever bigger.

Revision r2 arrived in July 2024 at the IBM Quantum Developer Conference. It expanded the lattice from 133 to 156 qubits and introduced a technique for reducing the effect of two-level-system defects, a common source of noise in superconducting devices. In 2024 IBM showed that a 100-qubit circuit of depth 100, which contains roughly 5,000 two-qubit gates in the instance described, could be run on Heron within hours, completing a challenge it had set itself at the 2022 Summit. Revision r3 followed in 2025.

How it works

Heron uses fixed-frequency transmon qubits, but it places a separate, tunable coupler element between each pair of neighbors. A coupler is a small superconducting circuit whose frequency can be adjusted with a flux pulse. When the coupler is tuned one way, the two qubits do not interact; when it is tuned another way, they interact strongly enough to perform a two-qubit gate in a few hundred nanoseconds. This is a different design from the cross-resonance gates used in Eagle, Osprey, and Condor.

The qubits are arranged on a heavy-hex lattice, and IBM's software, Qiskit, handles the task of mapping a user's circuit onto this layout, inserting swap gates when needed. Because noise remains significant, IBM provides error suppression and error mitigation options in its Runtime service. Techniques such as dynamical decoupling, twirling, and zero-noise extrapolation run additional circuits to estimate what the noiseless answer would have been, at the price of more shots and longer run time.

Median two-qubit error has fallen as calibration and design improved. In 2024 a Heron-class device moved from about 0.5% median error to about 0.3% following updated calibrations, and the best individual qubit pairs do better. IBM's longer-term plan is to push median error toward 0.1% or lower on future chips, which is closer to what error correction needs.

Connectivity

Heavy-hex: each qubit connects to two or three neighbors through tunable couplers

Specifications in detail

Key features

• Tunable couplers that switch interactions between qubits on and off, cutting crosstalk
• Three to five times better error performance than the Eagle generation
• Revision r2 (July 2024) grew to 156 qubits and added mitigation of two-level-system defects
• Runs 100-qubit, depth-100 circuits (about 5,000 two-qubit gates) in hours with error mitigation
• Used in IBM Quantum System Two installations

Limitations

• 156 qubits is small next to Condor or neutral atom machines
• Two-qubit error rates are still above the levels needed for cheap error correction
• Heavy-hex connectivity requires swap operations for many algorithms
• Results on noisy hardware depend on error mitigation, which increases the number of shots required

Timeline

What it is used for

• Utility-scale experiments on spin models and materials, often with error mitigation
• Teaching and prototyping quantum algorithms on a real device through IBM Quantum
• Research into error mitigation, benchmarking, and hybrid quantum-classical workflows
• Early quantum-centric supercomputing experiments linking quantum chips with classical HPC

How it compares

• Compared with IBM Eagle and Osprey, Heron has fewer or similar qubits but much lower error rates, thanks to tunable couplers.
• Compared with Google Willow, Heron has more qubits but a higher median two-qubit error; Willow focuses on error-correction experiments, Heron on broad cloud access.
• Compared with trapped-ion systems such as IonQ Forte and Quantinuum H2, Heron has much faster gates but lower fidelity and less flexible connectivity.

Technical notes

Heron's headline feature is the tunable coupler. In earlier IBM chips the interaction between neighboring qubits was always on, so qubits slowly disturbed each other even when idle. In Heron the coupling can be turned off except when a gate is applied, which reduces spectator errors. IBM's own measurements showed the original Heron at about one fifth the error of Eagle on comparable benchmarks.

Why it matters

Heron is where most people meet IBM hardware. It is the chip behind a large share of published utility-scale experiments from IBM and its partners, and its performance sets the practical baseline for what cloud users can run today.

The move from fixed couplings to tunable couplers is also a clear example of how hardware design, not just qubit count, drives progress. Many of the ideas in Heron carry into IBM's newer Nighthawk and Loon chips.

Frequently asked questions

Keep exploring

• Company profile: IBM
• Related processor: IBM Condor
• Related processor: IBM Eagle
• Related processor: IBM Osprey
• Related processor: Google Willow

This profile is written for educational purposes and summarizes company announcements, published papers, and vendor specification sheets. Last reviewed: September 30, 2026. Figures marked as company-reported have not all been independently verified, and benchmarks differ between vendors, so compare them with care.

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